LTC2641/LTC2642

16

26412f

Op Amp Specifications and Bipolar DAC Accuracy

The op amp contributions to unipolar DAC error discussed

above apply equally to bipolar operation. The bipolar ap-

plication circuit gains up the DAC span, and all errors, by

a factor of 2. Since the LSB size also doubles, the errors

in LSBs are identical in unipolar and bipolar modes.

bias current offset error becomes:

So:

V

I IN

k I IN

k

k

V

OFFSET

B

B

REF

=

()

+

() •

– (

) •

.

•

–

28

12 4

33

[]

LSB

Settling Time with Op Amp Buffer

When using an external op amp, the output settling time will

still include the single pole settling on the LTC2641/LTC2642

capacitance and PC board interconnect capacitance.

The external buffer amplifier adds another pole to the output

response, with a time constant equal to (fbandwidth/2

π).

83ns = 1μs/12. The output amplifier pole will also have a

time constant of 83ns if the closed-loop bandwidth equals

(1/2

π • 83ns) = 1.9MHz. The effective time constant of

two cascaded single-pole sections is approximately the

root square sum of the individual time constants, or √

⎯2

• 83ns = 117ns, and 1/2 LSB settling time will be ~12 •

117ns = 1.4μs. This represents an ideal case, with no slew

limiting and ideal op amp phase margin. In practice, it

will take a considerably faster amplifier, as well as careful

attention to maintaining good phase margin, to approach

the unbuffered settling time of 1μs.

The output settling time for bipolar applications (Figure 3)

will be somewhat increased due to the feedback resistor

A small feedback capacitor, C1, should be included, to

introduce a zero that will partially cancel this pole. C1

to 10pF. This will restore the phase margin and improve

coarse settling time, but a pole-zero doublet will unavoid-

ably leave a slower settling tail, with a time constant of

time to be greater than 2μs.

Reference and GND Input

The LTC2641/LTC2642 operates with external voltage refer-

can be maintained if appropriate guidelines are followed

when selecting and applying the reference. The LTC2641/

LTC2642’s very low gain error tempco of 0.1ppm/°C, typi-

cal, corresponds to less than 0.5LSB variation over the

–40°C to 85°C temperature range. In practice, this means

that the overall gain error tempco will be determined almost

entirely by the external reference tempco.

The DAC voltage-switching mode “inverted” resistor ladder

architecture used in the LTC2641/LTC2642 exhibits a refer-

300k at code 0000hex (zero scale). The maximum change

occurs near midscale, the INL error is about one half of the

requires a reference load regulation of (1.53ppm • 2/160μA)

= 19 [ppm/mA]. This implies a reference output impedance

of 48m

Ω, including series wiring resistance.

To prevent output glitches from occuring when resistor

input must maintain low impedance at higher frequencies.

A 0.1μF ceramic capacitor with short leads between REF

and GND provides high frequency bypassing. A surface

mount ceramic chip capacitor is preferred because it has

the lowest inductance. An additional 1μF between REF

and GND provides low frequency bypassing. The circuit

will benefit from even higher bypass capacitance, as long

as the external reference remains stable with the added

capacative loading.

APPLICATIONS INFORMATION