MPC8358E datasheet(21/96 Pages) FREESCALE

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MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1

Freescale Semiconductor

DDR and DDR2 SDRAM

MDQ/MECC/MDM output setup with respect to MDQS

266 MHz

200 MHz

tDDKHDS,

tDDKLDS

1.0

1.2

—ns

MDQ/MECC/MDM output hold with respect to MDQS

266 MHz

200 MHz

tDDKHDX,

tDDKLDX

1.0

1.2

—ns

MDQS preamble start

tDDKHMP

-0.5

× tMCK – 0.6

-0.5

× tMCK + 0.6

MDQS epilogue end

tDDKHME

–0.6

0.9

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock Control

address/command valid with the rising edge of MCK.

4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the

ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks

by 1/2 applied cycle.

5. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing

(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through

control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to

the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these

2 parameters have been set to the same adjustment value. See the

MPC8360E Integrated Communications Processor

Reference Manual, Rev. 2 for a description and understanding of the timing modifications enabled by use of these bits.

6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the device.

7. All outputs are referenced to the rising edge of MCK(n) at the pins of the device. Note that tDDKHMP follows the symbol

conventions described in note 1.

8. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.

Table 19. DDR and DDR2 SDRAM Output AC Timing Specifications for Source Synchronous Mode

(continued)

Parameter 8

Symbol 1

Min

Max

Unit

Notes

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