ADS5413

SLWS153 − DECEMBER 2003

www.ti.com

12

APPLICATION INFORMATION

CONVERTER OPERATION

The ADS5413 is a 12-bit pipeline ADC. Its low power

(400 mW) at 65 MSPS and high sampling rate is achieved

using a state-of-the-art switched capacitor pipeline

architecture built on an advanced low-voltage CMOS

process. The ADS5413 analog core operates from a 3.3 V

supply consuming most of the power. For additional

interfacing flexibility, the digital output supply (OVDD) can

be set from 1.6 V to 3.6 V. The ADC core consists of 10

pipeline stages and one flash ADC. Each of the stages

produces 1.5 bits per stage. Both the rising and the falling

clock edges are utilized to propagate the sample through

the pipeline every half clock, for a total of six clock cycles.

ANALOG INPUTS

The analog input for the ADS5413 consists of a differential

track-and-hold amplifier implemented using a switched

capacitor technique, shown in Figure 27. This differential

input topology, along with closely matched capacitors,

produces a high level of ac-performance up to high

sampling and input frequencies.

The ADS5413 requires each of the analog inputs (VINP

and VINM) to be externally biased around the common

mode level of the internal circuitry (CML, pin 6).

For a full-scale differential input, each of the differential

lines of the input signal (pins 3 and 4) swings symmetrically

between CML+(Vreft+Vrefb)/2 and CML−(Vreft+Vrefb)/2.

The maximum swing is determined by the difference

between the two reference voltages, the top reference

(REFT), and the bottom reference (REFB). The total

differential full-scale input swing is 2(Vreft − Vrefb). See

the reference circuit section for possible adjustments of

the input full scale.

Although the inputs can be driven in single-ended

configuration,

the

ADS5413

obtains

optimum

performance

when

the

analog

inputs

are

driven

differentially. The circuit in Figure 30 shows one possible

configuration. The single-ended signal is fed to the primary

of an RF transformer. Since the input signal must be

biased around the common-mode voltage of the internal

circuitry, the common-mode (CML) reference from the

ADS5413 is connected to the center-tap of the secondary.

To ensure a steady low noise CML reference, the best

performance is obtained when the CML output is

connected to ground with a 0.1-

µF and 0.01-µF low

inductance capacitor.

R

VINP

VCM

ADS5413

0.01

µF

0.1

µF

Z0 = 50 Ω

1:1

VINN

50

Ω

AC Signal

Source

T1-1T

R0

50

Ω

Figure 30. Driving the ADS5413 Analog Input

With Impedance Matched Transmission Line

If it is necessary to buffer or apply a gain to the incoming

analog signal, it is possible to combine a single-ended

amplifier with an RF transformer as shown in Figure 31.

Texas Instruments offers a wide selection of operational

amplifiers, as the THS3001/2, the OPA847, or the OPA695

that can be selected depending on the application. RIN and

CIN can be placed to isolate the source from the switching

inputs of the ADC and to implement a low-pass RC filter to

limit the input noise in the ADC. Although not needed, it is

recommended to lay out the circuit with placement for

those three components, which allows fine tune of the

prototype if necessary. Nevertheless, any mismatch

between the differential lines of the input produces a

degradation in performance at high input frequencies,

mainly characterized by an increase in the even

harmonics. In this case, special care should be taken

keeping as much electrical symmetry as possible between

both inputs. This includes shorting RIN and leaving CIN

unpopulated.

RT

+

−

OPA690

AIN−

AIN+

5 V

CML

R1

0.1

µF

RS

ADS5413

RIN

CIN

RIN

0.1

µF

1:n

−5 V

R2

VIN

Figure 31. Converting a Single-Ended Input Signal Into a Differential Signal Using an RF Transformer