CD74HCT574Q1

HIGHSPEED CMOS LOGIC OCTAL DTYPE FLIPFLOP

3STATE, POSITIVEEDGE TRIGGERED

SCLS570A − FEBRUARY 2004 − REVISED APRIL 2008

6

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.3 V

3 V

3 V

0 V

0 V

th

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Data Input

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

3 V

0 V

1.3 V

1.3 V

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

Output

Control

Output

Waveform 1

S1 at VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

≈VCC

0 V

1.3 V

10%

1.3 V

≈0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open Drain

Open

VCC

GND

VCC

TEST

S1

3 V

0 V

1.3 V

tw

VOLTAGE WAVEFORMS

PULSE DURATION

Input

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 1 MHz, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.

D. The outputs are measured one at a time, with one input transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

F. tPLH and tPHL are the same as tpd.

G. tPLZ and tPHZ are the same as tdis.

H. tPZH and tPZL are the same as ten.

From Output

Under Test

CL

(see Note A)

LOAD CIRCUIT FOR

3-STATE AND OPEN-DRAIN OUTPUTS

S1

VCC

RL = 1 kΩ

GND

From Output

Under Test

CL

(see Note A)

Test

Point

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Open

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

90%

Figure 1. Load Circuit and Voltage Waveforms