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M25PE16-VMP6TP 数据表(PDF) 45 Page - STMicroelectronics |
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M25PE16-VMP6TP 数据表(HTML) 45 Page - STMicroelectronics |
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45 / 56 page ![]() M25PE16 Reset 45/56 8 Reset Driving Reset (RESET) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost. All the Lock bits are reset to 0 after a RESET Low pulse. Table 12 shows the status of the device after a RESET Low pulse. 9 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each Byte contains FFh). All usable Status Register bits are 0. Table 12. Device status after a RESET Low pulse Conditions: Reset pulse occurred Lock bits status Internal logic status Addressed data While decoding an instruction(1): WREN, WRDI, RDID, RDSR, READ, RDLR, Fast_Read, WRLR, PW, PP, PE, SE, BE, SSE, DP, RDP 1. S remains Low while RESET is Low. Reset to 0 Same as POR Not significant Under completion of an Erase or Program cycle of a PW, PP, PE, SSE, SE, BE operation Reset to 0 Equivalent to POR Addressed data could be modified Under completion of a WRSR operation Reset to 0 Equivalent to POR (after tW) Write is correctly completed Device deselected (S High) and in Standby mode Reset to 0 Same as POR Not significant |
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