ADL5541

Rev. 0 | Page 10 of 12

BASIC CONNECTIONS

The basic connections for operating the ADL5541 are shown in

Figure 13. Recommended components are listed in Table 5. The

input and output should be ac-coupled with appropriately sized

capacitors (device characterization was performed with 33 pF

capacitors). A 5 V dc bias is supplied to the amplifier via GND

(Pin 6) and through a biasing inductor connected to RFOUT

(Pin 8). The bias voltage should be decoupled using a 1 μF

capacitor, a 1.2 nF capacitor, and two 68 pF capacitors.

VCC

3GND

6

GND

4CB

5

VPOS

1RFIN

8

RFOUT

2GND

7

GND

ADL5541

C4

68pF

C5

1.2nF

C6

1µF

VCC

C2

33pF

C1

33pF

RFIN

RFOUT

L1

47nH

C3

1µF

GND

C7

68pF

Figure 13. Basic Connections

For operation between 50 MHz and 500 MHz, a larger biasing

choke and ac coupling capacitors are necessary (see Table 5).

Figure 14 shows a plot of the input return loss, the output

return loss and the gain with these components. At 100 MHz,

tone). The noise figure performance for operation from 50

MHz to 500 MHz is shown in Figure 15. When operating below

50 MHz, the ADL5541 exhibits gain peaking, and the input and

output match degrade significantly.

17.0

12.0

50

500

FREQUENCY (MHz)

16.5

16.0

15.5

15.0

14.5

14.0

13.5

13.0

12.5

–5

–30

–10

–15

–20

–25

100

150

200

250

300

350

400

450

S11

S21

S22

Figure 14. Input Return Loss (S11), Output Return Loss (S22), and

Gain (S21) vs. Frequency

4.5

2.0

50

500

FREQUENCY (MHz)

4.0

3.5

3.0

2.5

100

150

200

250

300

350

400

450

Figure 15. Noise Figure vs. Frequency from 50 MHz to 500 MHz

SOLDERING INFORMATION AND RECOMMENDED

PCB LAND PATTERN

Figure 16 shows the recommended land pattern for the ADL5541.

To minimize thermal impedance, the exposed paddle on the

package underside should be soldered down to a ground plane

along with Pin 2, Pin 3, Pin 6, and Pin 7. If multiple ground

layers exist, they should be stitched together using vias (a

minimum of five vias is recommended). For more information

on land pattern design and layout, refer to Application Note

AN-772, A Design and Manufacturing Guide for the Lead Frame

Chip Scale Package (LFCSP).

PIN 1

PIN 4

PIN 8

PIN 5

1.85mm

2.03mm

1.78mm

0.5mm

0.71mm

1.53mm

Figure 16. Recommended Land Pattern

Table 5. Recommended Components for Basic Connections

Frequency

C1

C2

C3

L1

C4

C5

C6

C7

50 MHz to 500 MHz

0.1 μF

0.1 μF

1 μF

470 nH (Coilcraft 0603LS-471-NX or equivalent)

68 pF

1.2 nF

1 μF

68 pF

500 MHz to 6000 MHz

33 pF

33 pF

1 μF

47 nH (Coilcraft 0603CS-47-NX or equivalent)

68 pF

1.2 nF

1 μF

68 pF