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SLG51003 数据表(PDF) 39 Page - Renesas Technology Corp

部件名 SLG51003
功能描述  PMIC with High PSRR, Low Noise, Multi-Output LDOs and Integrated Load Switch
PDF  72 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

SLG51003 数据表(HTML) 39 Page - Renesas Technology Corp

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SLG51003 Datasheet
R16DS0379EU0100, Rev. 1.00
Sep 12, 2024
Page 39
There are two possible methods for clearing the event registers controlled by OTP bit I2C_CLR_MODE (register
SYSCTL_SYS_CONF_D).
▪
CLR_MODE (= 0): each event or fault log register bit is cleared either when it is read or by writing a 1 to
each bit. In this mode, the
‘read’ clears the entire register. This is the default mode.
▪
CLR_MODE (= 1): each event or fault log register bit is only cleared by writing a 1 to each bit.



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