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PCF8563T/5 数据表(PDF) 20 Page - NXP Semiconductors

部件名 PCF8563T/5
功能描述  Real-time clock/calendar
PDF  45 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8563T/5 数据表(HTML) 20 Page - NXP Semiconductors

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PCF8563
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 11 — 26 October 2015
20 of 45
NXP Semiconductors
PCF8563
Real-time clock/calendar
[1]
Registers marked x are undefined at power-up and unchanged by subsequent resets.
8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speed up on-board test of the device. The setting of this
mode requires that the I2C-bus pins, SDA and SCL, are toggled in a specific order as
shown in Figure 12. All timings are required minimums.
Once the override mode has been entered, the device immediately stops, being reset,
and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus
access. The override mode may be cleared by writing logic 0 to TESTC. TESTC must be
set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0
during normal operation has no effect except to prevent entry into the POR override
mode.
Table 27.
Register reset value[1]
Address
Register name
Bit
7
6
5
4
3
2
1
0
00h
Control_status_1
00001000
01h
Control_status_2
00000000
02h
VL_seconds
1
xxxxxxx
03h
Minutes
xxxxxxxx
04h
Hours
xxxxxxxx
05h
Days
xxxxxxxx
06h
Weekdays
xxxxxxxx
07h
Century_months
xxxxxxxx
08h
Years
xxxxxxxx
09h
Minute_alarm
1
xxxxxxx
0Ah
Hour_alarm
1
xxxxxxx
0Bh
Day_alarm
1
xxxxxxx
0Ch
Weekday_alarm
1
xxxxxxx
0Dh
CLKOUT_control
1
xxxxx0
0
0Eh
Timer_control
0
xxxxx1
1
0Fh
Timer
xxxxxxxx
Fig 12. POR override sequence
mgm664
SCL
500 ns
2000 ns
SDA
8 ms
override active
power-on



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