PCF8563

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© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 11 — 26 October 2015

7 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

8.3 Control registers

8.3.1 Register Control_status_1

[1]

Default value.

[2]

Bits labeled as N should always be written with logic 0.

8.3.2 Register Control_status_2

Alarm registers

09h

Minute_alarm

AE_M

MINUTE_ALARM (0 to 59)

0Ah

Hour_alarm

AE_H

x

HOUR_ALARM (0 to 23)

0Bh

Day_alarm

AE_D

x

DAY_ALARM (1 to 31)

0Ch

Weekday_alarm

AE_W

xxxxWEEKDAY_ALARM (0 to 6)

CLKOUT control register

0Dh

CLKOUT_control

FE

xxxxxFD[1:0]

Timer registers

0Eh

Timer_control

TE

xxxxxTD[1:0]

0Fh

Timer

TIMER[7:0]

Table 4.

Formatted registers overview …continued

Bit positions labelled as x are not relevant. Bit positions labelled with N should always be written with logic 0; if read they

could be either logic 0 or logic 1. After reset, all registers are set according to Table 27.

Address

Register name

Bit

7

6

5

4

3

2

1

0

Table 5.

Control_status_1 - control and status register 1 (address 00h) bit description

Bit

Symbol

Value

Description

Reference

7

TEST1

0[1]

normal mode

must be set to logic 0 during normal operations

Section 8.9

1

EXT_CLK test mode

6N

0[2]

unused

5STOP

0[1]

RTC source clock runs

Section 8.10

1

all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC

clock is stopped (CLKOUT at 32.768 kHz is still available)

4N

0[2]

unused

3

TESTC

0

Power-On Reset (POR) override facility is disabled; set to logic 0 for

normal operation

Section 8.11.1

1[1]

Power-On Reset (POR) override may be enabled

2to0

N

000[2]

unused

Table 6.

Control_status_2 - control and status register 2 (address 01h) bit description

Bit

Symbol

Value

Description

Reference

7to5

N

000[1]

unused

4TI_TP

0[2]

INT is active when TF is active (subject to the status of TIE)

Section 8.3.2.1

and

Section 8.8

1INT pulses active according to Table 7 (subject to the status of TIE);

Remark: note that if AF and AIE are active then INT will be

permanently active