74ACT161

SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

December 1998

s

HIGH SPEED:

s

LOW POWER DISSIPATION:

s

COMPATIBLE WITH TTL OUTPUTS

s

50

Ω TRANSMISSION LINE DRIVING

CAPABILITY

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 161

s

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The

ACT161

is

a

high-speed

CMOS

SYNCRONOUS

PRESETTABLE

COUNTER

fabricated with sub-micron silicon gate and

double-layer metal wiring C

ideal for low power applications mantaining high

speed operation similar to eqivalent Bipolar

Schottky TTL. It is a 4 bit binary counter with

Asynchronous Clear.

The circuit have four fundamental modes of

operation, in order of preference: synchronous

reset, parallel load, count-up and hold. Four

control inputs, Master Reset (CLEAR), Parallel

Enable Input (LOAD), Count Enable Input (PE)

and Count Enable Carry Input (TE), determine

the mode of operation as shown in the Truth

Table. A LOW signal on CLEAR overrides

counting and parallel loading and sets all outputs

on LOW state. A LOW signal on LOAD overrides

counting and allows information on Parallel Data

Qn inputs to be loaded into the flip-flops on the

next rising edge of CLOCK. With LOAD and

CLEAR, PE and TE permit counting when both

are HIGH. Conversely, a LOW signal on either

PE and TE inhibits counting.

The device is designed to interface directly High

Speed CMOS systems with TTL, NMOS and

CMOS output voltage levels.

All inputs

and

outputs are

equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

M

(Micro Package)

B

(Plastic Package)

ORDER CODES :

74ACT161B

74ACT161M

®

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