INPUT AND OUTPUT EQUIVALENT CIRCUIT

LOGIC DIAGRAM

PIN DESCRIPTION

PIN No

SYMBOL

NAME AND F UNCTIO N

1

CLEAR

Asyncronous Master Reset

(Active LOW)

2, 5, 7, 10,

12, 15

Q0 to Q5

Flip-Flop Outpus

3, 4, 6, 11,

13, 14

D0 to D5

Data Inputs

9

CLOCK

Clock Input (LOW-to-HIGH,

Edge- Triggered)

8

GND

Ground (0V)

16

Positive Supply Voltage

TRUTH TABLE

INPUTS

O UTPUTS

FUNCTI ON

CL EAR

D

CLOCK

Q

L

X

X

L

CLEAR

HL

L

HH

H

HX

NO CHANGE

X: Don’t Care

This logic diagram has not be used to estimate propagation delays

74ACT174

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