LP3992

EN

OUT

GND

CAP

IN

VIN

VEN

VOUT

1 PF

1 PF

COUT

CIN

High= ON

Low= OFF

LP3992

SNVS192C – OCTOBER 2002 – REVISED NOVEMBER 2015

www.ti.com

9 Application And Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LP3992 can provide 30-mA output current with 1.9-V to 5.2-V input. It is stable with 1-

μF ceramic input and

output capacitors. Typical output noise is 300

μVRMS at frequencies from 10 Hz to 100 kHz. Typical power supply

rejection is 40 dB at 1 kHz.

9.2 Typical Application

Figure 15. LP3992 Typical Application

9.2.1 Design Requirements

For typical CMOS voltage regulator applications, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Minimum input voltage

1.9 V

Output voltage

1.5 ± 0.09 V

Output current

30 mA

9.2.2 Detailed Design Procedure

9.2.2.1

External Capacitors

In common with most regulators, the LP3992 requires external capacitors for regulator stability. The device is

specifically designed for portable applications requiring minimum board space and smallest components. These

capacitors must be correctly selected for good performance.

12

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