A/

NA

S

'0'

Slave Address

(7 bits)

Control Register Add.

(8 bits)

A

A

Data- Data

(8 bits)

P

R/W

Data transfered, byte +

Ack/NAck

Sr

Slave Address

(7 bits)

'1' A

R/W

Direction of the transfer

will change at this point

From Master to Slave

From Slave to Master

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

Sr - REPEATED START CONDITION

Register Read Format

NA - ACKNOWLEDGE (SDA High)

S

'0'

Slave Address

(7 bits)

Control Register Add.

(8 bits)

A

A

A

Register Data

(8 bits)

P

R/W

From Master to Slave

From Slave to Master

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

Data transfered,

byte + Ack

Register Write Format

LP8553

SNVS701B – SEPTEMBER 2011 – REVISED JANUARY 2014

www.ti.com

•

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

•

Slave sends acknowledge signal if the slave address is correct.

•

Slave sends data byte from addressed register.

•

If the master device sends acknowledge signal, the control register address will be incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

Table 1. Data Read and Write Cycles

Address Mode

<Start Condition>

<Slave Address><r/w = 0>[Ack]

<Register Addr.>[Ack]

<Repeated Start Condition>

Data Read

<Slave Address><r/w = 1>[Ack]

[Register Data]<Ack or NAck>

… additional reads from subsequent register address possible

<Stop Condition>

<Start Condition>

<Slave Address><r/w=’0’>[Ack]

<Register Addr.>[Ack]

Data Write

<Register Data>[Ack]

… additional writes to subsequent register address possible

<Stop Condition>

<>Data from master [ ] Data from slave

Register Read and Write Detail

24

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