INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

PIN No

SYMBOL

NAME AND F UNCTION

1, 19

S0, S1

Mode Select Inputs

2, 3

G1, G2

3 State Output Enable Inputs (Active LOW)

7, 13, 6, 14, 5, 15, 4, 16

A/QA to H/QH

Parallel Data Inputs or 3 State Parallel Outputs (Bus Driver)

8, 17

QA’ to QH’

Serial Outputs (Standard Output)

9

CLEAR

Asynchronous Master Reset Input (Active LOW)

11

SR

Serial Data Shift Right Input

12

CLOCK

Clock Input (LOW to HIGH, Edge-triggered)

18

SL

Serial Data Shift Left Input

10

GND

Ground (0V)

20

Positive Supply Voltage

TRUTH TABLE

MO DE

INPUTS

I NPUTS/ OUTPUTS

O UT PUT S

CLEAR

F UNCTIO N

SELECTED

OUTPUT

CONTRO L

CLO CK

SERI AL

A/Q A

H/Q H

QA’

QH’

S1

S0

G1*

G2*

SL

SR

Z

L

HHX

X

X

X

X

Z

Z

L

L

CLEAR

L

L

X

L

L

X

X

X

LLLL

L

X

LLL

X

X

X

LLLL

HOLD

H

LLLL

X

X

X

QA0

QH0

QA0

QH0

SHIFT

RIGHT

H

L

H

L

L

X

H

H

QGn

H

QGn

H

L

H

L

L

X

L

L

QGn

L

QGn

SHIFT

LEFT

H

H

L

L

L

H

X

QBn

H

QBn

H

H

H

L

L

L

L

X

QBn

L

QBn

L

LOAD

H

H

H

X

X

X

X

ahah

* When one or both output controls are high, the eight, input/output terminals arethe high impedanc e state: howewer sequential operation or clearing of

the register is not affected.

Z

: HIGH IMPEDANCE

Qn0 : THE LEVELOF An BEFORE THE INDICATED STEADYSTATEINPUTCONDITIONS WERE ESTABLISED.

Qnn : THE LEVELOF Qn BEFORETHE MOST RECENTACTIVETRANSITIONINDICATEDBY OR

a,h : THE LEVELOF THE STEADYSTATEINPUTSA, H, RESPECTIVELY.

X

: DON’T CARE

74ACT299

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