74ACT280

9 BIT PARITY GENERATOR/CHECKER

®

December 1998

s

s

LOW POWER DISSIPATION:

s

COMPATIBLE WITH TTL OUTPUTS

s

50

Ω TRANSMISSION LINE DRIVING

CAPABILITY

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 280

s

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The AC280 is an advanced high-speed CMOS 9

BIT

PARITY

GENERATOR

-

CHECKER

fabricated with sub-micron silicon gate and

double-layer metal wiring C

ideal for low power applications mantaining high

speed operation similar to eqivalent Bipolar

Schottky TTL.

It is composed of nine data inputs (A to I) and

odd/even parity outputs (

ΣODD and ΣEVEN). The

nine data inputs control the output conditions.

When the number of high level input is odd,

ΣODD output is kept high and ΣEVEN output low.

Conservely, when the output is even,

ΣEVEN

output is kept high and

ΣODD low.

The IC generates either odd or even parity

making it flexible application.

The word-length capability is easily expanded by

cascading.

The device is designed to interface directly High

Speed CMOS systems with TTL, NMOS and

CMOS output voltage levels.

All inputs

and

outputs are

equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

ORDER CODES :

74ACT280B

74ACT280M

M

(Micro Package)

B

(Plastic Package)

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