PCM1723

8

SBAS057A

www.ti.com

FIGURE 7. Audio Data Input Timing.

using a crystal oscillator. The PLL will directly track any

variations in the master clock frequency, and jitter on the

system clock is specified at 250ps maximum. Figure 3 illus-

trates the timing requirements for the 27MHz master clock.

Figure 4 illustrates the system clock connections for an

external clock or crystal oscillator.

The PCM1723 internal PLL can be programmed for nine

different sampling frequencies (LRCIN), as shown in Table

I. The internal sampling clocks generated by the various

programmed frequencies are shown in Table II. The system

clock output frequency for the PCM1723 is 100% accurate.

To provide MCKO clock and SCKO clock for external

circuit, external buffer circuit is effective to avoid degrading

audio performance.

SPECIAL FUNCTIONS

The PCM1723 includes several special functions, including

digital attenuation, digital de-emphasis, soft mute, data for-

mat selection and input word resolution. These functions are

controlled using a three-wire interface. MD (pin 8) is used

for the program data, MC (pin 7) is used to clock in the

program data, and ML (pin 6) is used to latch in the program

data. Table III lists the selectable special functions.

FUNCTION

DEFAULT MODE

Input Audio Data Format Selection

Normal Format

Normal Format

I2S Format

Input Audio Data Bit Selection

16/20/24 Bits

16 Bits

Input LRCIN Polarity Selection

Lch/Rch = High/Low

Lch/Rch = High/Low

Lch/Rch = Low/High

De-emphasis Control

OFF

Soft Mute Control

OFF

Attenuation Control

0dB

Lch, Rch Individually

Lch, Rch Individually Fixed

Lch, Rch Common

Infinite Zero Detection Circuit Control

OFF

Operation Enable (OPE)

Enabled

Sample Rate Selection

Internal System Clock Selection

256fS

384fS

384fS

Double Sampling Rate Selection

Standard Sampling Rate—44.1/48/32kHz

Standard Sampling Rate

Double Sampling Rate—88.2/96/32kHz

Half Sampling Rate—22.05/24/16kHz

Sampling Frequency

44.1kHz Group

44.1kHz

48kHz Group

32kHz Group

Analog Output Mode

L, R, Mono, Mute

Stereo

TABLE III. Selectable Functions.

Sampling Frequencies-LRCIN (kHz)

Half of Standard Sampling Freq

16

22.05

24

Standard Sampling Freq

32

44.1

48

Double of Standard Sampling Freq

64

88.2

96

TABLE I. Sampling Frequencies.

Sampling

Frequency

System Clock

System Clock

(LRCIN)

256fS

384fS

16kHz

Half

4.096MHz

6.144MHz

32kHz

Standard

8.192MHz

12.288MHz

64kHz

Double

16.384MHz

24.576MHz

22.05kHz

Half

5.6448MHz

8.4672MHz

44.1kHz

Standard

11.2896MHz

16.9344MHz

88.2kHz

Double

22.5792MHz

33.8688MHz

24kHz

Half

6.144MHz

9.216MHz

48kHz

Standard

12.288MHz

18.432MHz

96kHz

Double

24.576MHz

36.864MHz

TABLE II. Sampling Frequencies vs Internal System

Clock (= Output Frequencies of PLL).

LRCKIN

BCKIN

DIN

1.4V

1.4V

1.4V

t

BCH

t

BCL

t

LB

t

BL

t

DS

BCKIN Pulse Cycle Time

BCKIN Pulse Width High

BCKIN Pulse Width Low

BCKIN Rising Edge to LRCIN Edge

LRCIN Edge to BCKIN Rising Edge

DIN Set-up Time

DIN Hold Time

: t

BCY

: t

BCH

: t

BCL

: t

BL

: t

LB

: t

DS

: t

DH

: 100ns (min)

: 50ns (min)

: 50ns (min)

: 30ns (min)

: 30ns (min)

: 30ns (min)

: 30ns (min)

t

DH

t

BCY