MIC5166 datasheet(20/36 Pages) MICROCHIP

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MIC5166

DS20006085B-page 20

 2018 - 2019 Microchip Technology Inc.

6.0

PCB LAYOUT GUIDELINES

To minimize EMI and output noise, follow these layout

recommendations.

PCB layout is critical to achieve reliable, stable, and

efficient performance. A ground plane is required to

control EMI and minimize the inductance in power,

signal, and return paths.

The following guidelines should be followed to ensure

proper operation of the MIC5166 converter.

6.1

• The 10 µF ceramic capacitor, which is connected

to the VIN pin, must be located right at the IC. The

VDDQ pin is very noise sensitive and placement

of the capacitor is very critical. Use wide traces to

connect to the VDDQ and AGND pins.

• The signal ground pin (AGND) must be connected

directly to the ground planes. Do not route the

AGND pin to the PGND Pad on the top layer.

• Place the IC close to the point-of-load (POL).

• Use wide traces to route the input and output

power lines.

• Signal and power grounds should be kept

separate and connected at only one location.

6.2

Input Capacitor

• A 10 µF X5R or X7R dielectric ceramic capacitor

is recommended on each of the VIN pins for

bypassing.

• Place the input capacitors on the same side of the

board and as close to the IC as possible.

• Keep both the VIN pin and PGND connections

short.

• Place several vias to the ground plane close to

the input capacitor ground terminal.

• Use either X7R or X5R dielectric input capacitors.

Do not use Y5V or Z5U type capacitors.

• Do not replace the ceramic input capacitor with

any other type of capacitor. Any type of capacitor

can be placed in parallel with the input capacitor.

• If a Tantalum input capacitor is placed in parallel

with the input capacitor, it must be recommended

for switching regulator applications and the

operating voltage must be derated by 50%.

• In hot-plug applications, a Tantalum or Electrolytic

bypass capacitor must be used to limit the

overvoltage spike seen on the input supply with

power is suddenly applied.

6.3

Output Capacitor

• Use a wide trace to connect the output capacitor

ground terminal to the input capacitor ground

terminal.

• Phase margin will change as the output capacitor

value and ESR changes. Contact the factory if the

output capacitor is different from what is shown in

the BOM.

• The feedback divider network must be place close

to the IC with the bottom of R2 connected to

AGND.

• The feedback trace should be separate from the

power trace and connected as close as possible

to the output capacitor. Sensing a long high

current load trace can degrade the DC load

regulation.

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