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XCVU29P 数据表(PDF) 12 Page - Advanced Micro Devices

部件名 XCVU29P
功能描述  Virtex UltraScale FPGA Data Sheet: DC and AC Switching Characteristics
PDF  68 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

XCVU29P 数据表(HTML) 12 Page - Advanced Micro Devices

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I/O Levels
Table 8: SelectIO DC Input and Output Levels for I/O Banks
I/O Standard1, 2, 3
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Max
V, Min
mA
mA
HSTL_I
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300
0.400
VCCO – 0.400
5.8
–5.8
HSTL_I_12
–0.300
VREF – 0.080
VREF + 0.080
VCCO + 0.300
25% VCCO
75% VCCO
4.1
–4.1
HSTL_I_18
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300
0.400
VCCO – 0.400
6.2
–6.2
HSUL_12
–0.300
VREF – 0.130
VREF + 0.130
VCCO + 0.300
20% VCCO
80% VCCO
0.1
–0.1
LVCMOS12
–0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.400
VCCO – 0.400
Note 4
Note 4
LVCMOS15
–0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.450
VCCO – 0.450
Note 5
Note 5
LVCMOS18
–0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.450
VCCO – 0.450
Note 5
Note 5
LVDCI_15
–0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.450
VCCO – 0.450
7.0
–7.0
LVDCI_18
–0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.450
VCCO – 0.450
7.0
–7.0
SSTL12
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300
VCCO/2 – 0.150
VCCO/2 + 0.150
8.0
–8.0
SSTL135
–0.300
VREF – 0.090
VREF + 0.090
VCCO + 0.300
VCCO/2 – 0.150
VCCO/2 + 0.150
9.0
–9.0
SSTL15
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300
VCCO/2 – 0.175
VCCO/2 + 0.175
10.0
–10.0
SSTL18_I
–0.300
VREF – 0.125
VREF + 0.125
VCCO + 0.300
VCCO/2 – 0.470
VCCO/2 + 0.470
7.0
–7.0
MIPI_DPHY_ DCI_LP6
–0.300
0.550
0.880
VCCO + 0.300
0.050
1.100
0.01
–0.01
Notes:
1.
Tested according to relevant specifications.
2.
Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide
(UG571).
3.
POD10 and POD12 DC input and output levels are shown in Table 9, Table 13, and Table 14.
4.
Supported drive strengths of 2, 4, 6, or 8 mA in I/O banks.
5.
Supported drive strengths of 2, 4, 6, 8, or 12 mA in I/O banks.
6.
Low-power option for MIPI_DPHY_DCI.
Table 9: DC Input Levels for Single-ended POD10 and POD12 I/O Standards
I/O Standard1, 2
VIL
VIH
V, Min
V, Max
V, Min
V, Max
POD10
–0.300
VREF – 0.068
VREF + 0.068
VCCO + 0.300
POD12
–0.300
VREF – 0.068
VREF + 0.068
VCCO + 0.300
Notes:
1.
Tested according to relevant specifications.
2.
Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide
(UG571).
Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
DS923 (v1.10) April 26, 2019
www.xilinx.com
Product Specification
12
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