STM32F412RGH3PTR datasheet(40/201 Pages) STMICROELECTRONICS

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Functional overview

STM32F412xE/G

40/201

DocID028087 Rev 7

3.30

Secure digital input/output interface (SDIO)

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory

Card Specification Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus

modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack

of MMC4.1 or previous.

In addition to SD/SDIO/MMC/eMMC, this interface is fully compliant with the CE-ATA digital

protocol Rev1.1.

3.31

Controller area network (bxCAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1

Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as

extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive

FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). 256 byte of SRAM are allocated for each CAN.

3.32

Universal serial bus on-the-go full-speed (USB_OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated

transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and

with the OTG 1.0 specification. It has software-configurable endpoint setting and supports

suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock

that is generated by a PLL connected to the HSE oscillator. The Battery Charging Detection

(BCD) can detect and identify the type of port, it is connected to (standard USB or charger).

The type of charging is also detected: Dedicated Charging Port (DCP), Charging

Downstream Port (CDP) and Standard Downstream Port (SDP). Some packages provide a

dedicated USB power rail allowing a different supply for the USB and for the rest of the chip.

For instance the chip can be powered with the minimum specified supply and the USB

running at the level defined by the standard. The major features are:

•

Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing

•

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

•

6 bidirectional endpoints

•

12 host channels with periodic OUT support

•

HNP/SNP/IP inside (no need for any external resistor)

•

For OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

•

Link Power Management (LPM)

•

Battery Charging Detection (BCD) supporting DCP, CDP and SDP

STM32F412RGH3PTR 数据表(PDF) 40 Page - STMicroelectronics

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