TUSB2136 datasheet(15/53 Pages) TI

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2−2

I2C bus, or the host can be used via the USB. On device reset, the SDW bit (in the ROM register) and the CONT bit

in the USB control register (USBCTL) are cleared. This configures the memory space to boot mode (see memory

map, Table 2−2) and keeps the device disconnected from the host.

The first instruction is fetched from location 0000 (which is in the 6K ROM). The 8K RAM is mapped to XDATA space

(location 0000h). The MCU executes a read from an external EEPROM and tests to see if it contains the code (test

for boot signature). If it contains the code, the MCU reads from EEPROM and writes to the 8K RAM in XDATA space.

If not, the MCU proceeds to boot from USB.

Once the code is loaded, the MCU sets SDW to 1. This switches the memory map to normal mode, i.e. the 8K RAM

is mapped to code space, and the MCU starts executing from location 0000h. Once the switch is done, the MCU sets

CONT to 1 (in the USBCTL register) This connects the device to the USB, resulting in the normal USB device

enumeration.

2.2.2

MCNFG: MCU Configuration Register

This register is used to control the MCU clock rate.

210

RSV

XINT

OVCE

SDW

R/W

R/O

R/W

BIT

NAME

RESET

FUNCTION

SDW

This bit enables/disables boot ROM.

SDW

SDW = 0

When clear, the MCU executes from the 6K boot ROM space. The boot ROM appears in two

locations: 0000 and 8000h. The 8K RAM is mapped to XDATA space; therefore, read/write

operation is possible. This bit is set by the MCU after the RAM load is completed. The MCU

cannot clear this bit. It is cleared on power-up reset or function reset.

SDW = 1

When set by MCU, the 6K boot ROM maps to location 8000h, and the 8K RAM is mapped to

code space, starting at location 0000h. At this point, the MCU executes from RAM, and write

operation is disabled (no write operation is possible in code space).

4−1

R[3:0]

No effect

These bits reflect the device revision number.

OVCE

Hub overcorrect detection enable/disable bit.

OVCE

OVCE = 0

Hub overcorrect detection is disabled.

OVCE = 1

Hub overcorrect detection is enabled.

XINT

INT1 source control bit

XINT

XINT = 0

INT1 is connected to the P3.3 pin and operates as a standard INT1 interrupt.

XINT = 1

INT1 is connected to the OR of port-2 inputs.

RSV

Reserved

2.2.3

PUR_n: GPIO Pullup Register for Port n (n = 0 to 3)

PUR_0: GPIO pullup register for port 0

PUR_1: GPIO pullup register for port 1

PUR_2: GPIO pullup register for port 2

PUR_3: GPIO pullup register for port 3

PORT_n.7

PORT_n.6

PORT_n.5

PORT_n.4

PORT_n.3

PORT_n.2

PORT_n.1

PORT_n.0

R/W

BIT

NAME

RESET

FUNCTION

0−7

PORT_n.N

(N = 0 to 7)

The MCU can write to this register. If the MCU sets this bit to 1, the pullup resistor is disconnected from

the pin. If the MCU clears this bit to 0, the pullup resistor is connected to the pin. The pullup resistor is

connected to the VCC power supply.

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