STM32F412RGJ3P datasheet(21/201 Pages) STMICROELECTRONICS

21 / 201 page

DocID028087 Rev 7

21/201

STM32F412xE/G

Functional overview

3.8

Embedded SRAM

All devices embed 256 Kbyte of system SRAM which can be accessed (read/write) at CPU

clock speed with 0 wait states

3.9

Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves

(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient

operation even when several high-speed peripherals work simultaneously.

Figure 5. Multi-AHB matrix

3.10

DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8

streams each. They are able to manage memory-to-memory, peripheral-to-memory and

memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,

support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is

needed when the controller reaches the end of the buffer. The two DMA controllers also

have a double buffering feature, which automates the use and switching of two memory

buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software

trigger on each stream. Configuration is made by software and transfer sizes between

source and destination are independent.

STM32F412RGJ3P 数据表(PDF) 21 Page - STMicroelectronics