STM32F412RGY7 datasheet(39/201 Pages) STMICROELECTRONICS

39 / 201 page

DocID028087 Rev 7

39/201

STM32F412xE/G

Functional overview

The DFSDM peripheral supports:

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4 multiplexed input digital serial channels:

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configurable SPI interface to connect various SD modulator(s)

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configurable Manchester coded 1 wire interface support

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PDM (Pulse Density Modulation) microphone input support

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maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)

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clock output for SD modulator(s): 0...20 MHz

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alternative inputs from 4 internal digital parallel channels (up to 16 bit input resolution):

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internal sources: device memory data streams (DMA)

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2 digital filter modules with adjustable digital signal processing:

–Sincx filter: filter order/type (1...5), oversampling ratio (up to 1...1024)

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integrator: oversampling ratio (1...256)

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up to 24-bit output data resolution, signed output data format

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automatic data offset correction (offset stored in register by user)

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continuous or single conversion

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start-of-conversion triggered by

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software trigger

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internal timers

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external events

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start-of-conversion synchronously with first digital filter module (DFSDM1FLT0)

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analog watchdog feature:

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low value and high value data threshold registers

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dedicated configurable Sincx digital filter (order = 1...3, oversampling ratio = 1...32

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input from digital output data or from selected input digital serial channels

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continuous monitoring independently from standard conversion

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short circuit detector to detect saturated analog input values (bottom and top range):

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up to 8-bit counter to detect 1...256 consecutive 0’s or 1’s on serial data stream

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monitoring continuously each input serial channel

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break signal generation on analog watchdog event or on short circuit detector event

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extremes detector:

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storage of minimum and maximum values of final conversion data

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refreshed by software

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DMA capability to read the final conversion data

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interrupts: end of conversion, overrun, analog watchdog, short circuit input serial

channel clock absence

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“regulator” or injected” conversions:

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“regular” conversions can be requested at any time or even in continuous mode

without having any impact on the timing of “injected” conversions

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“injected” conversions for precise timing and with high conversion priority.

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