SN74ACT74EP

DUAL POSITIVEEDGETRIGGERED DTYPE FLIPFLOP

WITH CLEAR AND PRESET

SCAS722 − OCTOBER 2003

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D Extended Temperature Performance of

−55

°C to 125°C

D Enhanced Diminishing Manufacturing

Sources (DMS) Support

D Enhanced Product-Change Notification

D Qualification Pedigree†

† Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

D 4.5-V to 5.5-V VCC Operation

D Inputs Accept Voltages to 5.5 V

D Max tpd of 10.5 ns at 5 V

D Inputs Are TTL-Voltage Compatible

description/ordering information

The SN74ACT74-EP is a dual positive-edge-triggered D-type flip-flop.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at D can be changed without affecting the levels at the outputs.

ORDERING INFORMATION

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−55

°C to 125°C

SOIC − D

Tape and reel

SN74ACT74MDREP

SACT74MEP

‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

LX

XL

H

L

LX

X

H§

H§

H

H

↑

HH

L

H

H

↑

LL

H

H

H

L

X

Q0

Q0

§ This configuration is nonstable; that is, it does not

persist when either PRE or CLR returns to its

inactive (high) level.

Copyright

 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1CLR

1D

1CLK

1PRE

1Q

1Q

GND

VCC

2CLR

2D

2CLK

2PRE

2Q

2Q

D PACKAGE

(TOP VIEW)