 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA

Appnote 49

www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178

2

May 31, 2000-14

Figure 1. Block diagram of A/D converter

Conversion of the sampled analog voltage takes place between the

6th and 15th machine cycle after sampling has been completed. In

the 15th machine cycle the converted result is moved to ADDAT.

Timer 2

The SAB 80515 has three 16-bit Timer/Counters: Timer 0, Timer 1

and Timer 2. These Timers can be configured to operate either as

Figure 2. Functional diagram of Timer 2 in reload mode

BD

7

CLK

6

–

5

BSY

4

ADM

3

MX2

2

MX1

1

MX0

0

Baud

Rate

Enable

System

Clock

Enable

Busy

Flag

Conver-

sion

Mode

Analog Input

Select

8-BIT

ADCON

8

76543210

8-BIT

DAPR

8

8

8

DIGITAL VALUE

FOR IVAREF

DIGITAL VALUE

FOR IVAGND

MSB

LSB

VAREF

VAGND

4-BIT D/A

CONVERTER

4-BIT D/A

CONVERTER

8-BIT A/D

CONVERTER

4

4

8-BIT ADDAT

S & H

MUX

AN0 – AN7

I

N

T

E

R

N

A

L

B

U

S

ANALOG

I/P

ANALOG VALUE

FOR IVAREF

ANALOG VALUE

FOR IVAGND

REF+

REF–

Input

clock

≥ 1

Timer 2

Interrupt

Request

Compare/Reload/Capture Register

TL2

TH2

T2EX

P 1.5

Mode 1

Mode 0

Reload

CRCL

Low Byte

CRCH

High Byte

TF 2

EXF 2

EXEN 2

timers or event counters. Timer 2 is the time base of the

programmable Timer/Counter Register Array (PTRA) unit.

In addition to the operational modes “Timer” or “counter”,

Timer 2, being the time base for the PTRA unit, provides

the features of:

—16-bit reload

—16-bit compare

—16-bit capture

The reload mode of Timer 2 is used in this application to

generate software delays. For explanation of the other

modes please refer to the users’ manual.

Reload

The reload mode for Timer 2 is selected by bits T2R0 and

T2R1 in special function register T2CON as illustrated in

Table 1. In mode 0, when Timer 2 rolls over from all 1s to

all 0s, it not only sets TF2 but also causes the Timer 2 reg-

isters to be loaded with the 16-bit value in the CRC (com-

pare/reload/capture) register which is preset by software.

The reload will happen in the same machine cycle in which

TF2 is set, thus overwriting the count value 0000H.

Table 1. Timer 2 reload mode selection

PD2435

The PD2435 is a CMOS 4-character 5x7 dot matrix alpha-

numeric programmable display with ROM to decode 128

ASCII alphanumeric characters and enough RAM to store

the display’s complete four digit ASCII message with soft-

ware programmable attributes. The CMOS IC incorporates

special interface control circuitry to allow the user to

control the module as a fully supported microprocessor

peripheral.

Microprocessor Interface

The interface to the microprocessor is through the address

lines (A0-A2), the data bus (D0-D7), two chip select lines

(CE0, CE1), and (RD) and (WR) lines. The CE0 should be

held low and CE1 held high when executing a read or write

to a specific PD243X device. The read and write lines

are both active low. A valid write will enable the data as

input lines.

Programming the PD2435

There are five registers within the PD2435. Four of the reg-

isters are used to hold the ASCII code of the four display

characters. The fifth register is the Control Word, which is

used to blink, blank, clear or dim the entire display to

change the presentation (attributes) of individual

characters.

T2RI

T2R0

Mode

0

X

Reload Disabled

1

0

Mode 0: Auto-Reload upon Timer 2

Overflow (TF2)

1

1

Mode 1: Reload upon Falling Edge at

Pin T2EX/P1.5