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SN74LVC652APWR 数据表(PDF) 2 Page - Texas Instruments

部件名 SN74LVC652APWR
功能描述  OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
PDF  20 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

SN74LVC652APWR 数据表(HTML) 2 Page - Texas Instruments

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN54LVC652A, SN74LVC652A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS303L – JANUARY 1993 – REVISED SEPTEMBER 2005
These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB
and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. A low input selects real-time data, and a high input selects stored data. Figure 1
illustrates the four fundamental bus-management functions that are performed with the 'LVC652A devices.
Data on the A or B data bus, or both, is stored in the internal D-type flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by
simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other
data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sinking/current-sourcing capability of the driver.
FUNCTION TABLE
INPUTS
DATA I/O(1)
OPERATION OR FUNCTION
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
A1–A8
B1–B8
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
↑
↑
X
X
Input
Input
Store A and B data
X
H
↑
H or L
X
X
Input
Unspecified(2)
Store A, hold B
H
H
↑
↑
X(2)
X
Input
Output
Store A in both registers
L
X
H or L
↑
X
X
Unspecified(2)
Input
Hold A, store B
L
L
↑
↑
X
X(2)
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
Stored A data to B bus and
H
L
H or L
H or L
H
H
Output
Output
stored B data to A bus
(1)
The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always
are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
(2)
Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers.
2



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