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STM32F207IET6 数据表(PDF) 29 Page - STMicroelectronics |
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STM32F207IET6 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 184 page  DocID15818 Rev 15 29/184 STM32F20xxx Functional overview 183 Figure 7. Regulator OFF/internal reset OFF The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains (see Figure 8). • PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.08 V, and until VDD reaches 1.7 V. • NRST should be controlled by an external reset controller to keep the device under reset when VDD is below 1.7 V (see Figure 9). In this mode, when the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. • The brownout reset (BOR) circuitry is disabled. • The embedded programmable voltage detector (PVD) is disabled. • VBAT functionality is no more available and VBAT pin should be connected to VDD. |
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