X24C01A

6

Current Address Read

Internally the X24C01A contains an address counter that

maintains the address of the last word accessed,

incremented by one. Therefore, if the last access (either a

read or write) was to address n, the next read operation

would access data from address n + 1. Upon receipt of the

slave address with R/W set to one, the X24C01A

issues an acknowledge and transmits the eight bit word

during the next eight clock cycles. The read operation is

terminated by the master; by not responding with an

acknowledge and by issuing a stop condition. Refer to

Figure 7 for the sequence of address, acknowledge and data

transfer.

Random Read

Random read operations allow the master to access any

memory location in a random manner. Prior to issuing

the slave address with the R/W bit set to one, the master must

first perform a “dummy” write operation. The master issues

issues the start condition, and the slave address followed

by the word address it is to read. After the word

address acknowledge, the master immediately reissues the

start condition and the slave address with the R/W bit set to

one. This will be followed by an acknowledge from the

X24C01A and then by the eight bit word. The read operation

is terminated by the master; by not responding with an

acknowledge and by issuing a stop condition.

Refer to Figure 8 for the address, acknowledge and data

transfer sequence.

Figure 7. Current Address Read

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24C01A

S

T

A

R

T

SLAVE

ADDRESS

S

S

T

O

P

P

A

C

K

DATA

3841 FHD F12

Figure 8. Random Read

3841 FHD F13

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24C01A

S

T

A

R

T

SLAVE

ADDRESS

S

A

C

K

S

T

A

R

T

S

WORD

ADDRESS n

A

C

K

SLAVE

ADDRESS

DATA n

A

C

K

S

T

O

P

P