74VHC238

3 TO 8 LINE DECODER

June 1999

s

s

LOW POWER DISSIPATION:

s

HIGH NOISE IMMUNITY:

s

POWER DOWN PROTECTION ON INPUTS

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 238

s

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74VHC238 is an advanced high-speed

CMOS 3 TO 8 LINE DECODER fabricated with

sub-micron silicon gate and double-layer metal

wiring C

If the device is enabled, 3 binary select inputs (A,

B and C) determine which one of the outputs will

go high. If enable input G1 is held low or either

G2A or G2B is held high, decoding function is

inhibited and all the 8 outputs go to low.

Three enable inputs are provided to ease

cascade connection and application of this

address decoders for memory systems.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs

and

outputs are

equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

M1

(Micro Package)

T

(TSSOP Package)

ORDER CODES :

74VHC238M

74VHC238T

®

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