STM32F427NET6XXX datasheet(181/231 Pages) STMICROELECTRONICS

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STM32F427xx STM32F429xx

Electrical characteristics

192

NAND controller waveforms and timings

Figure 69 through Figure 72 represent synchronous waveforms, and Table 100 and

Table 101 provide the corresponding timings. The results shown in this table are obtained

with the following FMC configuration:

•

COM.FMC_SetupTime = 0x01;

•

COM.FMC_WaitSetupTime = 0x03;

•

COM.FMC_HoldSetupTime = 0x02;

•

COM.FMC_HiZSetupTime = 0x01;

•

ATT.FMC_SetupTime = 0x01;

•

ATT.FMC_WaitSetupTime = 0x03;

•

ATT.FMC_HoldSetupTime = 0x02;

•

ATT.FMC_HiZSetupTime = 0x01;

•

Bank = FMC_Bank_NAND;

•

MemoryDataWidth = FMC_MemoryDataWidth_16b;

•

ECC = FMC_ECC_Enable;

•

ECCPageSize = FMC_ECCPageSize_512Bytes;

•

TCLRSetupTime = 0;

•

TARSetupTime = 0.

In all timing tables, the THCLK is the HCLK clock period.

Table 99. Switching characteristics for PC Card/CF read and write cycles

in I/O space(1)(2)

Symbol

Parameter

Min

Max

Unit

tw(NIOWR)

FMC_NIOWR low width

8THCLK − 0.5

tv(NIOWR-D)

FMC_NIOWR low to FMC_D[15:0] valid

th(NIOWR-D)

FMC_NIOWR high to FMC_D[15:0] invalid

9THCLK − 2-

td(NCE4_1-NIOWR) FMC_NCE4_1 low to FMC_NIOWR valid

5THCLK

th(NCEx-NIOWR)

FMC_NCEx high to FMC_NIOWR invalid

5THCLK

-ns

td(NIORD-NCEx)

FMC_NCEx low to FMC_NIORD valid

5THCLK

th(NCEx-NIORD)

FMC_NCEx high to FMC_NIORD) valid

6THCLK+2

tw(NIORD)

FMC_NIORD low width

8THCLK − 0.5

8THCLK+0.5

tsu(D-NIORD)

FMC_D[15:0] valid before FMC_NIORD high

THCLK

-ns

td(NIORD-D)

FMC_D[15:0] valid after FMC_NIORD high

1. CL = 30 pF.

2. Guaranteed by characterization results.

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