THS1007

SLAS286B − AUGUST 2000− REVISED DECEMBER 2010

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24

Test Mode

The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown

in Table 10.

Table 10. Test Mode

BIT 9

TEST1

BIT 8

TEST0

OUTPUT RESULT

0

0

Normal mode

0

1

VREFP

1

0

((VREFM)+(VREFP))/2

1

1

VREFM

Three different options can be selected. This feature allows support testing of hardware connections between

the ADC and the processor.

Control Register 1, Write Only (see Table 7)

BIT 11

BIT10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

1

RESERVED

OFFSET

BIN/2s

R/W

RES

RES

RES

RES

SRST

RESET

Table 11. Control Register 1 Bit Functions

BITS

RESET

VALUE

NAME

FUNCTION

0

0

RESET

Reset

Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values.

To bring the device out of RESET, a 0 has to be written into this bit.

1

0

SRST

Writing a 1 into this bit resets the sync generator. When running in multichannel mode, this must be set during the

configuration cycle.

2, 3

0,0

RES

Reserved

4

1

RES

Reserved

5

1

RES

Reserved

6

0

R/W

R/W, RD/WR selection

Bit 6 of control register 1 controls the function of the inputs RD and WR. Whenbit 6 in control register 1 is set to

1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with

R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR

becomes a write input.

7

0

BIN/2s

Complement select

If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of

control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 2 through Table 5.

8

0

OFFSET

Offset cancellation mode

Bit 8 = 0 → normal conversion mode

Bit 8 = 1 → offset calibration mode

If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conver-

sion. The conversion result is stored in an offset register and subtracted from all conversions in order to

reduce the offset error.

9

0

RESERVED Always write 0.