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74VHC273 数据表(PDF) 4 Page - STMicroelectronics

部件名 74VHC273
功能描述  OCTAL D-TYPE FLIP FLOP WITH CLEAR
PDF  10 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

74VHC273 数据表(HTML) 4 Page - STMicroelectronics

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CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
Val ue
Un it
TA =25
oC
-40 to 85
oC
Min.
Typ .
Max.
Min .
Max.
CIN
Input Capacitance
4
10
10
pF
CPD
Power Dissipation
Capacitance (note 1)
31
pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD
• VCC • fIN +ICC/8 (per Flip-Flop)
AC ELECTRICAL CHARACTERISTICS (Input tr =tf =3 ns)
Symb ol
Parameter
Test Co nditi on
Val ue
Un it
VCC
(V)
CL
(pF )
TA =25
oC
-40 to 85
oC
Min.
Typ .
Max.
Min .
Max.
tPLH
tPHL
Propagation Delay
Time
CK to Q
3.3
(*)
15
8.7
13.6
1.0
16.0
ns
3.3
(*)
50
11.2
17.1
1.0
19.5
5.0
(**)
15
5.8
9.0
1.0
10.5
5.0
(**)
50
7.3
11.0
1.0
12.5
tPHL
Propagation Delay
Time
CLR to Q
3.3
(*)
15
8.9
13.6
1.0
16.0
ns
3.3
(*)
50
11.4
17.1
1.0
19.5
5.0
(**)
15
5.2
8.5
1.0
10.0
5.0
(**)
50
6.7
10.5
1.0
12.0
tw
CLR pulse Width
LOW
3.3
(*)
5.0
6.0
ns
5.0
(**)
5.0
5.0
tw
CK pulse Width
HIGH or LOW
3.3
(*)
5.5
6.5
ns
5.0
(**)
5.0
5.0
ts
Setup Time D to CK
HIGH or LOW
3.3
(*)
5.5
6.5
ns
5.0
(**)
4.5
4.5
th
Hold Time D to CK
HIGH or LOW
3.3
(*)
1.0
1.0
ns
5.0
(**)
1.0
1.0
tREM
Removal Time
CLR to CK
3.3
(*)
2.5
2.5
ns
5.0
(**)
2.0
2.0
fMAX
Maximum Clock
Frequency
3.3
(*)
15
75
120
65
MHz
3.3
(*)
50
50
75
45
5.0
(**)
15
120
165
100
5.0
(**)
50
80
110
70
tOSLH
tOSHL
Output to Output Skew
Time (note 1)
3.3
(*)
50
1.5
1.5
ns
5.0
(**)
50
1.0
1.0
(*) Voltage range is 3.3V
± 0.3V
(**) Voltage range is 5V
± 0.5V
Note 1: Parameter guaranteed by design. tsoLH =|tpLHm-tpLHn|, tsoHL =|tpHLm -tpHLn|
74VHC273
4/10



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