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74VHC374 数据表(PDF) 4 Page - STMicroelectronics

部件名 74VHC374
功能描述  OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING
PDF  10 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

74VHC374 数据表(HTML) 4 Page - STMicroelectronics

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CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
Val ue
Un it
TA =25
oC
-40 to 85
oC
Min.
Typ .
Max.
Min .
Max.
CIN
Input Capacitance
4
10
10
pF
COUT
Output Capacitance
6
pF
CPD
Power Dissipation
Capacitance (note 1)
32
pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD
• VCC • fIN +ICC/8 (per Flip-Flop)
AC ELECTRICAL CHARACTERISTICS (Input tr =tf =3 ns)
Symb ol
Parameter
Test Co nditi on
Val ue
Un it
VCC
(V)
CL
(pF )
TA =25
oC
-40 to 85
oC
Min.
Typ .
Max.
Min .
Max.
tPLH
tPHL
Propagation Delay
Time
CK to Q
3.3
(*)
15
8.1
12.7
1.0
15.0
ns
3.3
(*)
50
10.6
16.2
1.0
18.5
5.0
(**)
15
5.4
8.1
1.0
9.5
5.0
(**)
50
6.9
10.1
1.0
11.5
tPZL
tPZH
Output EnableTime
3.3
(*)
15
RL =1K
Ω
7.1
11.0
1.0
13.0
ns
3.3
(*)
50
RL =1K
Ω
9.6
14.5
1.0
16.5
5.0
(**)
15
RL =1K
Ω
5.1
7.6
1.0
9.0
5.0
(**)
50
RL =1K
Ω
6.6
9.6
1.0
11.0
tPLZ
tPHZ
Output Disable Time
3.3
(*)
50
RL =1K
Ω
10.2
14.0
1.0
16.0
ns
5.0
(**)
50
RL =1K
Ω
6.1
8.8
1.0
10.0
tw
Clock Pulse Width
HIGH or LOW
3.3
(*)
5.0
5.5
ns
5.0
(**)
5.0
5.0
ts
Setup Time D to CK
HIGH or LOW
3.3
(*)
4.5
4.5
ns
5.0
(**)
3.0
3.0
th
Hold Time D to CK
HIGH or LOW
3.3
(*)
2.0
2.0
ns
5.0
(**)
2.0
2.0
fMAX
Maximum Clock
Frequency
3.3
(*)
60
250
60
MHz
5.0
(**)
100
270
100
tOSLH
tOSHL
Output to Output Skew
Time (note 1)
3.3
(*)
50
1.5
1.5
ns
5.0
(**)
50
1.0
1.0
(*) Voltage range is 3.3V
± 0.3V
(**) Voltage range is 5V
± 0.5V
Note 1: Parameter guaranteed by design. tsoLH =|tpLHm-tpLHn|, tsoHL =|tpHLm -tpHLn|
74VHC374
4/10



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