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STM32F427NET7 数据表(PDF) 185 Page - STMicroelectronics

部件名 STM32F427NET7
功能描述  ARM Cortex-M4 32b MCUFPU, 225DMIPS, up to 2MB Flash/2564KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera & LCD-TFT
PDF  231 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F427NET7 数据表(HTML) 185 Page - STMicroelectronics

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STM32F427xx STM32F429xx
Electrical characteristics
192
Table 102. SDRAM read timings(1)(2)
1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK.
2. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
2THCLK − 0.5
2THCLK+0.5
ns
tsu(SDCLKH _Data)
Data input setup time
2
-
th(SDCLKH_Data)
Data input hold time
0
-
td(SDCLKL_Add)
Address valid time
-
1.5
td(SDCLKL- SDNE)
Chip select valid time
-
0.5
th(SDCLKL_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS)
SDNRAS valid time
-
0.5
th(SDCLKL_SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
0.5
th(SDCLKL_SDNCAS)
SDNCAS hold time
0
-
Table 103. LPSDR SDRAM read timings(1)(2)
1. CL = 10 pF.
2. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tW(SDCLK)
FMC_SDCLK period
2THCLK − 0.5
2THCLK+0.5
ns
tsu(SDCLKH_Data)
Data input setup time
2.5
-
th(SDCLKH_Data)
Data input hold time
0
-
td(SDCLKL_Add)
Address valid time
-
1
td(SDCLKL_SDNE)
Chip select valid time
-
1
th(SDCLKL_SDNE)
Chip select hold time
1
-
td(SDCLKL_SDNRAS
SDNRAS valid time
-
1
th(SDCLKL_SDNRAS)
SDNRAS hold time
1
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
1
th(SDCLKL_SDNCAS)
SDNCAS hold time
1
-



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