PIC12LF1501 datasheet(155/352 Pages) MICROCHIP

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DS40001607D-page 155

PIC16(L)F1503

The I2C interface supports the following modes and

features:

•Master mode

• Slave mode

• Byte NACKing (Slave mode)

• Limited Multi-master support

• 7-bit and 10-bit addressing

• Start and Stop interrupts

• Interrupt masking

• Clock stretching

• Bus collision detection

• General call address matching

•Address masking

• Address Hold and Data Hold modes

• Selectable SDAx hold times

Figure 21-2 is a block diagram of the I2C interface mod-

ule in Master mode. Figure 21-3 is a diagram of the I2C

interface module in Slave mode.

FIGURE 21-2:

MSSPX BLOCK DIAGRAM (I2C™ MASTER MODE)

Note 1:

In devices with more than one MSSP

module, it is very important to pay close

attention to SSPxCONx register names.

SSPxCON1 and SSPxCON2 registers

control different operational aspects of

the same module, while SSPxCON1 and

SSP2CON1 control the same features for

two different modules.

Throughout this section, generic refer-

ences to an MSSPx module in any of its

operating modes may be interpreted as

being equally applicable to MSSPx or

MSSP2. Register names, module I/O sig-

nals, and bit names may use the generic

designator ‘x’ to indicate the use of a

numeral to distinguish a particular mod-

ule when required.

Read

Write

SSPxBUF

SSPxSR

Internal data

bus

Start bit, Stop bit,

Acknowledge

Generate

(SSPxCON2)

Baud Rate

Generator

(SSPxADD)

Shift clock

Start bit detected

Stop bit detected

Write collsion detect

Clock arbitration

State counter for end

of XMIT/RCV

Address match detect

SCLx in

Bus collision

MSb

LSb

SDAx

SCLx

SDAx in

Set/Reset: S, P, SSPxSTAT,

WCOL, SSPOV

Reset SEN, PEN (SSPxCON2)

Set SSPxIF, BCLxIF

[SSPM <3:0>]

Rev. 10-000077A

7/30/2013

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