SLAS367 datasheet(8/56 Pages) TI2

8 / 56 page

1–2

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Programmable Sampling Rate up to:

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Max 26 KSPS With On-Chip IIR/FIR Filter

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Max 104 KSPS With IIR/FIR Bypassed

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On-Chip FIR Produced 84-dB SNR for ADC and 91-dB SNR for DAC Over 13-kHz BW

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External DSPs IIR/FIR for a Final Sampling Rate of 8 Ksps (IIR/FIR Bypassed) Produced 87-dB SNR for

ADC and 92-dB SNR for DAC.

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Smart Time Division Multiplexed Serial Port (SMARTDM)

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Glueless 4-Wire Interface to DSP

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Automatic Cascade Detection (ACD) Self-Generates Master/Slave Device Addresses

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Programming Mode to Allow On-the-Fly Reconfiguration

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Continuous Data Transfer Mode to Support DSP’s DMA/Autobuffering Mode

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Turbo Mode to Maximize Bit Clock for Faster Data Transfer and Higher Data Bandwidth

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Total Number of Time Slots Dynamically Proportional to Number of Codecs in the Cascade to Eliminate

Unused Time Slots and Optimize DSP Memory Allocation

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Allows up to 16 Codecs to Be Connected to a Single Serial Port

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Host Port

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2-Wire Interface

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Selectable I2C or S2C

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Differential and Single-Ended Analog Input/Output

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Built-In Functions:

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Sidetone

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Antialiasing Filter (AAF)

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Programmable Input and Output Gain Control (PGA)

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Microphone Amplifiers

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Power Management With Hardware/Software Power-Down Modes 30

µW

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Separate Software Control for ADC and DAC Power Down

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Fully Compatible With TI C54x DSP Power Supplies

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1.65-V–1.95-V Digital Core Power

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1.1-V–3.6-V Digital I/O

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2.7-V–3.6-V Analog

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Power Dissipation (PD) 10 mW at 3 V in Standard Operation

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Internal Reference Voltage (Vref)

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2s Complement Data Format

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Test Mode Which Includes Digital Loopback and Analog Loopback

SLAS367 数据表(PDF) 8 Page - Texas Instruments

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