41 / 48 page
IP1001 LF
Data Sheet
41/48
Dec. 18, 2007
Copyright © 2006, IC Plus Corp.
IP1001-DS-R06
4.15
PHY Specific Control Register2 (Reg20)
Bit
Name
Description
Type
HW
Reset
SW
Reset
20[1:0]
SR_V/ SR_FAST Sew rate control parameters
RW
11
NA
20.2
Auto-crossover
Enable
1: Enable auto MDI/MDIX
0: Disable auto MDI/MDIX
RW
1
NA
20[5:3]
Reserved
The default value should be adopted for
normal operation.
R/W
101
NA
20.6
Speed10to100en
able
Detect the link partner’s speed change from
10BASE-T to 100BASE-TX by detecting
MLT3 signals
1: Enable
0: Disable
RW
1
NA
20[8: 7]
FIFO_Depth
FIFO depth latency
00: latency = 2
01: latency = 3
10: latency = 4
11: latency = 5
RW
10
NA
20.9
MDIX Enable
When disable auto-crossover
0: MDI
1: MDIX
RW
0
0
20.10
Reserved
The default value should be adopted for
normal operation.
R/W
1
NA
20.11
APS_ON
This bit is used to activate auto power saving
(APS) mode
0: Disable APS
1: Enable APS
RW
1
NA
20[15:12] Reserved
The default value should be adopted for
normal operation.
R/W
0000
NA
Register 21~31 are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
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