45 / 48 page
IP1001 LF
Data Sheet
5.3.3
GMII Timing
c. Transmit Timing Requirements
Symbol
Description
Min.
Typ.
Max.
Unit
TTXCLK
Period of transmit clock
-
8
-
ns
TXEN, TXD to GTX_CLK setup time
(TXPHASE_SEL=0, no clock delay added)
-0.65
ns
Ts2
TXEN, TXD to GTX_CLK setup time
(TXPHASE_SEL=1, clock delay added)
3.35
ns
TXEN, TXD to GTX_CLK hold time
(TXPHASE_SEL=0, no clock delay added)
0.2
ns
Th2
TXEN, TXD to GTX_CLK hold time
(TXPHASE_SEL=1, clock delay added)
4.2
ns
GTX_C LK
TXE N , TXD [7:0]
T s2
T h2
TTclk2
d. Receive Timing
Symbol
Description
Min.
Typ.
Max.
Unit
TRclk2
Period of receive clock
-
8
-
ns
RX_CLK rising edge to RXDV, RXD
(RXPHASE_SEL=0, no clock delay added)
0.4
ns
Td2
RX_CLK rising edge to RXDV, RXD
(RXPHASE_SEL=1, clock delay added)
4.4
ns
Td2
RX_CLK
RXDV, RXD[7:0]
TRclk2
Dec. 18, 2007
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Copyright © 2006, IC Plus Corp.
IP1001-DS-R06
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