IP1726LF-DS-R01 datasheet(17/33 Pages) ETC2

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IP1726 LF

Preliminary Data Sheet

17/33

Jun 15, 2005

IP1726 LF-DS-R06

The IP1726 LF can be enforced to run at a specified mode without referring to the PHY status. When

enforced, the IP1726 LF will write the forced mode to the corresponding PHY through MDC/MDIO and

poll the link status of PHY. Care should be taken that the operating mode in both MAC side and PHY side

should be consistent.

By programming the register 80H and 81H, the user can easily set the PHY register to a specified value.

Since the MDC runs at 2.5 Mhz clock speed, the CPU should check whether the current command has

been completed or not before issuing the next command. Bit 13 in the register 80H indicates the

progress of the read/write operation.

5.3

Programming the Internal Registers

There is no need to program the register of the IP1726 LF for the generic application. However it’s

probably necessary to program the internal register to fit some special applications. The interface

between the IP1726 LF and the CPU is a serial bus which comprises a clock and a I/O signal. Like the

access cycle of the serial management interface, the serial interface comprises the device ID, the

read/write command, the address and the data. The access cycle is depicted as below.

"0"

"1"

"0"

"1"

"0"

"Z"

"0" D15

D14

D13

........

SCPUC

SCPUIO

Fig. 5.1 The CPU read data from the IP1726

Driven by the CPU

Driven by the IP1726

"0"

"1"

"0"

"1"

"0"

D15

D14

D13

........

SCPUC

SCPUIO

Fig. 5.2 The CPU write data to the IP1726

Driven by the CPU

The access cycle is much like the access cycle of MDC, MDIO. Care should be taken that the switch ID

is 2-bit wide rather than 5-bit wide.

5.4

SS-SMII

The transmitter of the MAC transfers the transmit data to the PHY at the rising edge of TXCLK and the

TXSYNC indicates the start of the 10-bit frame. By recognizing the high pulse of the TXSYNC, the PHY

can capture the correct transmit data stream. The PHY transfers the receive data to the IP1726 LF in a

similar way. The difference is that the signal direction is reverse.

Accompanied by the high pulse of TXSYNC, the TXEN status is present on the TXDATA pin and then the

TX-ER status and finally 8-bit data. For the RX part of SS-SMII, the CRS(Carrier Sense) status is present

on the RXDATA during the high pulse of RXSYNC. The RX_DV(receive data valid) status follows CRS

and finally the 8-bit data.

For a given PHY port, the SS-SMII consists of six signals.

RXDATA-one bit data for receiver

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