20 / 36 page
IP101A LF
Data Sheet
20/36
Oct 22, 2007
Copyright © 2004, IC Plus Corp.
IP101A LF-DS-R12
Register Descriptions (continued)
Bit
Name
Description/Usage
Default value
(h): 0E00
Register 17 : PHY Interrupt Ctrl/Status Register
15
INTR pin used
Set high to enable pin48 as an interrupt pin. Pin48 will be
high impedance if this bit is set low.
0, R/W
14:12 Reserved
0, RO
11
All Mask
When this bit is set high, changes in all events will not cause
an interrupt
1, R/W
10
Speed Mask
When this bit is set high, changes in speed mode will not
cause an interrupt
1, R/W
9
Duplex Mask
When this bit is set high, changes in duplex mode will not
cause an interrupt
1, R/W
8
Link Mask
When this bit is set high, changes in link status will not cause
an interrupt
1, R/W
7
Arbiter State
Enable
When this bit is set low, changes in Auto-Negotiation arbiter
state machine will not cause an interrupt
0, R/W
6
Arbiter State
Change
Flag to indicate Auto-Negotiation arbiter change interrupt
0, RC
5:3
Reserved
0, RO
2
Link Status
Change
Flag to indicate link status change interrupt
0, RC
1
Speed Change
Flag to indicate speed change interrupt
0, RC
0
Duplex Change
Flag to indicate duplex change interrupt
0, RC
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
