IP1000A LF
Preliminary Data Sheet
54/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.2.2.11 InterruptLine
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x3C
Default Value ................ 0x00
Access Rule.................. Byte
Width ............................ 8 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
7..0
InterruptLine
Interrupt Line. InterruptLine specifies the interrupt
level used by the IP1000A LF. By setting
InterruptLine the host system may configure the
appropriate
interrupt
vector
for
its
Interrupt
Service Routine. For 80x86 processor based host
systems, InterruptLine corresponds to the IRQ
number (0x00 through 0x0F), with the value 0xFF
corresponding to disabled interrupts.
R/W
3.2.2.12 InterruptPin
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x3D
Default Value ................ 0x01
Access Rule.................. Byte
Width ............................ 8 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
7..0
InterruptPin
Interrupt Pin. InterruptPin indicates which PCI
interrupt signal the IP1000A LF will utilize. The
IP1000A LF always utilizes the INTAN interrupt
signal, corresponding to an InterruptPin value of
0x01.
R
3.2.2.13 IoBaseAddress
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x10
Default Value ................ 0x00000000
Access Rule.................. Double Word
Width ............................ 32 bits
The host uses IoBaseAddress to define the I/O base address for the IP1000A LF. PCI system requires
that I/O base addresses be set as if the host system used 32-bit I/O addressing. The upper 24 bits of
IoBaseAddress are accessible, indicating that the IP1000A LF requires 256 bytes in the host system I/O
address space.
When AsicCtrlRegister ForcedConfig[0] is 1, the IP1000A LF is in ForcedConfig Mode. In this mode, the
IO Base Address is loaded from EEPROM at offset 04’h(Upper Bytes), 05’h.
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