IP101A LF
Data Sheet
19/36
Oct 22, 2007
Copyright © 2004, IC Plus Corp.
IP101A LF-DS-R12
Register Descriptions (continued)
Bit
Name
Description/Usage
Default value
(h): 0000
Register 16 : PHY Spec. Control Register
15
Debug Mode
0 = IP101A LF operates at normal mode
1 = IP101A LF operates at debug mode
(Note: the functionalities of bit 16:<14:12>, and 16:<4:0>
depend on the setting of this bit 16:<15>)
0, R/W
14:12 Reserved
0, RO
11
Auto MDIX Off
Set high to disable the automatic switch of MDI and MDI-X
modes. If AN is disabled by setting pin37=0 during power
up, this bit will be set to 1 (Auto-MDIX off) automatically.
Setting Reg0.12=1 will re-activate AN, in this case, if user
needs Auto-MDIX function, this bit should be set to 0. For
details, please refer to section 7 Auto-MDIX function
description.
0, R/W
10
Heart Beat
Enable
Heart beat function enable at 10Base-T
0, R/W
9
Jabber Enable
Jabber function enable at 10Base-T
0, R/W
8
Far-End Fault
Enable/Disable
To enable or disable the functionality of Far-End Fault
Mode
Enable
Disable
100Base-TX
1
0
0, R/W
7
Analog Power
Saving Disable
Set high to disable the power saving during auto-negotiation
0, R/W
6
Reserved
0, RO
5
Bypass DSP
reset
Set high to bypass the reset DSP mechanism in PCS
sub-layer
0, R/W
4:3
Reserved
0, RO
2
Repeater Mode
Set high to put IP101A LF into repeater mode
0, R/W
1
APS Mode
Set high to enable Auto Power Saving mode
0, R/W
0
Analog Off
Set high to power down analog transceiver
0, R/W
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