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IP101A LF
Data Sheet
7.2
A.C. Characteristic
7.2.1
MII Timing
a.
Pin Reset and Clock output timing relationship
Symbol
Description
Min.
Typ.
Max.
Unit
Tdelay
Delay time after reset to clock output
-
40
-
us
MII_TXCLK
MII_RXCLK
T
delay
RESET_N
b. Transmit Timing Requirements
Symbol
Description
Min.
Typ.
Max.
Unit
TTxClk
Transmit clock period 100M MII
-
40
-
ns
TTxClk
Transmit clock period 10M MII
-
400
-
ns
TsTxClk
TXEN, TXD to MII_TXCLK setup time
2
-
-
ns
ThTxClk
TXEN, TXD to MII_TXCLK hold time
0.5
-
-
ns
MII_T XC LK
TXEN, TXD[3:0]
T sTxClk
T hTxClk
T TxClk
c.
Receive Timing
Symbol
Description
Min.
Typ.
Max.
Unit
TRxClk
Receive clock period 100M MII
-
40
-
ns
TRxClk
Receive clock period 10M MII
-
400
-
ns
TdRxClk
MII_RXCLK falling edge to RXDV, RXD
1
-
4
ns
TdRxClk
MII_RXCLK
RXDV, RXD[3:0]
TRxClk
Oct 22, 2007
32/36
Copyright © 2004, IC Plus Corp.
IP101A LF-DS-R12
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