IP1726 LF
Preliminary Data Sheet
16/33
Jun 15, 2005
Copyright © 2003, IC Plus Corp.
IP1726 LF-DS-R06
5
System Operation
5.1
Reset and EEPROM Download Procedure
The reset input should be kept at “0” for more than 1.6 microsecond after power up. After detecting the
rising edge of reset input, the IP1726 LF will start downloading the content of EEPROM(acting like an
EEPROM master).
The internal register address of the IP1726 LF should comply with the address of EEPROM. Being an
EEPROM master, the IP1726 LF will download the content of EEPROM with EEPROM ID “1726H”.
The mapping relationship between the IP1726 LF registers and the EEPROM address are depicted as
the following table.
EEPROM address
EEPROM content
IP1726 LF Register
00H
17H
XX
01H
26H
XX
02H
Expected value
01H[15:8]
03H
Expected value
01H[7:0]
04H
Expected value
02H[15:8]
05H
Expected value
02H[7:0]
••••••
••••••
••••••
••••••
••••••
••••••
FCH
Expected value
7EH[15:8]
FDH
Expected value
7EH[8:0]
Note:
1.
The EEPROM ID should be set to “3’b000”; i.e. A2=0; A1=0; A0=0
2.
The IP1726 LF download the content of the EEPROM ranging from address 00H to FDH; i.e. the
register beyond this range is not recognized by the IP1726 LF.
3.
The ID for IP1726 LF recognition should be set at address 00H and address 01H as stated in the
table.
5.2
Polling/Writing the PHY
The IP1726 LF periodically, around 2.8ms for each access cycle, read the status of the PHY through
MDC, MDIO management signals. The PHY registers that will be read/write are 0, 1, 4 and 5. After
reading the PHY status, the IP1726 LF will reconfigure the internal MAC to meet the operating mode of
the PHY.
The relationship between the port ID and the PHY ID is shown below.
IP1726 LF Port
ID
Port 1 to Port 24
Port 25
Port 26
PHY ID
address 8 to address 31
address 4
address 5
Comment
The
smallest
ID
of
the
IP1726
LF
corresponds to the smallest PHY ID.
Table 5.1 The Relationship between PHY ID and the IP1726 LF Port ID
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