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IP1726LF-DS-R06 数据表(PDF) 10 Page - List of Unclassifed Manufacturers

部件名 IP1726LF-DS-R06
功能描述  26-port 10/100M Smart Switch Controller
PDF  33 Pages
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

IP1726LF-DS-R06 数据表(HTML) 10 Page - List of Unclassifed Manufacturers

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IP1726 LF
Preliminary Data Sheet
10/33
Jun 15, 2005
Copyright © 2003, IC Plus Corp.
IP1726 LF-DS-R06
Pin description (continued)
Pin No.
Label
Type
Description
Power On setting. These pins will be latched upon reset (continued)
41
AGING_OFF
IL, PD Disable the MAC address table aging function
1: Disabled; 0: Enabled (Default)
43
HOME_VLAN_EN
IL, PD 1: Enable the home VLAN setting :
Port 1 ~ Port24 are all individual VLAN shared with 2
MII ports. For example, Port 1, port 25 and port 26 form
a VLAN group, etc.
1: Enabled; 0: Disabled (Default)
47, 45
TRUNK_0_ON[1:0]
IL, PD The trunk group 0 setting:
00 : no trunk (Default)
01 : port 1, 2 trunk-grouped
10 : port 1, 2, 3 trunk-grouped
11 : port 1, 2, 3, 4 trunk-grouped
54
BPDU_BCST_OFF
IL, PD Filter the packet with MAC destination address
01-80-c2-00-00-03~01-80-c2-00-00-0F
0 : Broadcast (Default)
1 : Filter
59
TAG_PRI_ON
IL, PD Enable 802.1Q TAG priority function of all ports
1:Enabled; 0: Disabled (Default)
61
IP_PRI_ON
IL, PD Enable IP TOS/DS priority function of all ports
1: Enable; 0: Disable (Default)
63
FAST_TEST_MODE
IL, PD Reserved for IC test.
108,107,94,93,
92,91
PORT_PRI_ON[5:0]
IL, PD Enable port base high priority function of port 1~ port 6
1: Enable; 0: Disable (Default)
110,109
WRR_RATIO_SET[1:0] IL, PD The ratio of the packet number for the weighted round
robin. The switch engine handles both priority queues
based on the ratio of the packet number defined below.
00 : First in first out (Default)
01 : 2/1
10 : 4/1
11 : 8/1
When these bits are set to “00”, the CoS priority will be void.
50, 26, 126
DELAY_SSSMII[2:0]
IL, PD The delay time of SS-SMII transmit data
delay_sssmii[0] : port 1~ port 8
delay_sssmii[1] : port 9~ port 16
delay_sssmii[2] : port 17~ port 24
1: 4ns delay; 0: no delay(Default)
Note:
1.
All the trapped pins are latched upon reset and are pulled down or pulled up by a 50K resistor inside
the chip.
2.
The designer can connect a 4.7K ohms resistor to set these pins to “1” or “0” to change the default
state.
3.
The content of an EEPROM will override the pin setting.



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