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IP178C/IP178C LF/IP178CH/IP178CH LF
Datasheet
2.12
Serial management interface
User can access IP178C/IP178CH’s MII registers through serial management interface with pin MDC
and MDIO. Its format is shown in the following table. To access MII register in IP178C/IP178CH, MDC
should be at least one more cycle than MDIO. That is, a complete command consists of 32 bits MDIO
data and at least 33 MDC clocks. When the SMI is idle, MDIO is in high impedance.
CPU
MDIO
178C
MDC
Syatem diagram
Frame
format
<Idle><start><op code><PHY address><Registers address><turnaround>
<data><idle>
Read
Operation
<Idle><01><10><A4A3A2A1A0><R4R3R2R1R0><Z0>
<b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1b0><Idle>
Write
Operation
<Idle><01><01><A4A3A2A1A0><R4R3R2R1R0><10>
<b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1b0><Idle>
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
1..1
idle
start
op
code
PHY address =
01h
Reg address =
00h
TA
Register data
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
idle
A
4
A
3
A
2
A
1
A
0
R
4
R
3
R
2
R
1
R
0
write
z
z
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
Z
0
0
0
0
0
1
0
0
0
0
0
1
1
0
idle
start
op
code
PHY address =
01h
Reg address =
00h
TA
Register data
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
idle
A
4
A
3
A
2
A
1
A
0
R
4
R
3
R
2
R
1
R
0
read
z
zz
MDC
MDIO
MDC
MDIO
1..1
1..1
1..1
47/93
June 21, 2007
Copyright © 2004, IC Plus Corp.
IP178Cx-DS-R12
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