74VHCT573A

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUT NON INVERTING

February 2000

s

s

LOW POWER DISSIPATION:

s

COMPATIBLE WITH TTL OUTPUTS:

s

POWER DOWN PROTECTION ON INPUTS &

OUTPUTS

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 573

s

IMPROVED LATCH-UP IMMUNITY

s

DESCRIPTION

The 74VHCT573A is an advanced high-speed

CMOS OCTAL D-TYPE LATCH with 3 STATE

OUTPUT

NON

INVERTING

fabricated with

sub-micron silicon gate and double-layer metal

wiring C

This 8 bit D-Type latch is controlled by a latch

enable input (LE) and an output enable input

(OE).

While the LE input is held at a high level, the Q

outputs will follow the data inputs precisely.

When the LE is taken low, the Q outputs will be

latched precisely at the logic level of D input data.

While the (OE) input is low, the 8 outputs will be

in a normal logic state (high or low logic level)

and while high level the outputs will be in a high

impedance state.

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage. This

device can be used to interface 5V to 3V.

All inputs

and

outputs are

equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

®

SOP

TSSOP

ORDER CODES

PACKAGE

T UBE

T & R

SOP

74VHCT573AM

74VHCT573AMTR

TSSOP

74VHCT573ATTR

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