ICS9DB202CF datasheet(1/13 Pages) IDT

部件名	ICS9DB202CF

功能描述	PCI EXPRESS JITTER ATTENUATOR

PDF	13 Pages

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制造商	IDT [Integrated Device Technology]

网页	http://www.idt.com

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PCI EXPRESS JITTER ATTENUATOR

ICS9DB202

IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR

1

ICS9DB202CG REV B JULY 14, 2006

GENERAL DESCRIPTION

The ICS9DB202 is a high perfromance 1-to-2

Differential-to-HCSL Jitter Attenuator designed for

use in PCI Express™ systems. In some PCI

Express™ systems, such as those found in desktop

PCs, the PCI Express™ clocks are generated from

a low bandwidth, high phase noise PLL frequency synthesizer.

In these systems, a jitter-attenuating device may be necessary

in order to reduce high frequency random and deterministic

jitter components from the PLL synthesizer and from the system

board. The ICS9DB202 has two PLL bandwidth modes. In low

bandwidth mode, the PLL loop bandwidth is 500kHz. This setting

offers the best jitter attenuation and is still high enough to pass

a triangular input spread spectrum profile. In high bandwidth

mode, the PLL bandwidth is at 1MHz and allows the PLL to

pass more spread spectrum modulation.

For serdes which have x10 reference multipliers instead of x12.5

multipliers, each of the two PCI Express™ outputs (PCIEX0:1)

can be set for 125MHz instead of 100MHz by configuring the

appropriate frequency select pins (FS0:1).

FEATURES

• Two 0.7V current mode differential HCSL output pairs

• One differential clock input

• CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum output frequency: 140MHz

• Input frequency range: 90MHz - 140MHz

• VCO range: 450MHz - 700MHz

• Output skew: 110ps (maximum)

• Cycle-to-cycle jitter: 110ps (maximum)

• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):

2.42ps (typical)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Available in both standard and lead-free RoHS compliant

packages

• Industrial temperature information available upon request

HiPerClockS™

ICS

PIN ASSIGNMENT

nOE0

nCLK

CLK

BYPASS

nOE1

PCIEXT0

nPCIEXC0

PCIEXT1

nPCIEXC1

BLOCK DIAGRAM

ICS9DB202

20-Lead TSSOP

6.50mm x 4.40mm x 0.92

package body

G Package

Top View

ICS9DB202

20-Lead, 209-MIL SSOP

5.30mm x 7.20mm x 1.75mm

body package

F Package

Top View

Phase

Detector

VCO

Loop

Filter

1 HiZ

0 Enabled

1 HiZ

0 Enabled

0 ÷4

1 ÷5

0 ÷5

1 ÷4

FS0

FS1

Internal Feedback

÷5

Current

Set

-

+

0

1

0

1

IREF

PLL_BW

CLK

nCLK

FS0

VDD

GND

PCIEXT0

PCIEXC0

VDD

nOE0

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

VDDA

BYPASS

IREF

FS1

VDD

GND

PCIEXT1

PCIEXC1

VDD

nOE1

类似零件编号 - ICS9DB202CF

制造商	部件名	数据表	功能描述
Integrated Circuit Syst...	ICS9DB202CF	263Kb / 11P	Two 0.7V current mode differential HCSL output pairs, 1 differential clock input REV. A OCTOBER 6, 2004
	ICS9DB202CFLF	263Kb / 11P	Two 0.7V current mode differential HCSL output pairs, 1 differential clock input REV. A OCTOBER 6, 2004
	ICS9DB202CFLFT	263Kb / 11P	Two 0.7V current mode differential HCSL output pairs, 1 differential clock input REV. A OCTOBER 6, 2004
	ICS9DB202CFT	263Kb / 11P	Two 0.7V current mode differential HCSL output pairs, 1 differential clock input REV. A OCTOBER 6, 2004

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