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TUSB4041IPAPRG4 数据表(PDF) 28 Page - Texas Instruments |
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TUSB4041IPAPRG4 数据表(HTML) 28 Page - Texas Instruments |
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28 / 48 page  28 TUSB4041I SLLSEK3E – JULY 2015 – REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TUSB4041I Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated 8.5.22 Additional Feature Configuration Register Offset = F0h Figure 23. Additional Feature Configuration Register 7 6 5 4 3 2 1 0 RSVD stsOutputEn pwronTime RSVD R-0 R/RW-0 R/W-0 R/W-0 Table 24. Additional Feature Configuration Register Field Descriptions Bit Field Type Reset Description 7:5 RSVD R 0 Reserved Read only, returns 0 when read. 4 RSVD R/RW 0 Reserved. 3:1 pwronTime RW 0 Power-on delay time When OTP ROM pwronTime field is all 0, this field sets the delay time from the removal disable of PWRCTL to the enable of PWRCTL when transitioning battery charging modes. For example, when disabling the power on a transition from a custom charging mode to dedicated charging port mode. The nominal timing is defined as follows: TPWRON_EN = (pwronTime + 1) x 200 ms (1) This field may be overwritten by EEPROM contents or by an SMBus host. 0 RSVD RW 0 Reserved 8.5.23 Device Status and Command Register Offset = F8h Figure 24. Device Status and Command Register 7 6 5 4 3 2 1 0 RSVD smbusRst cfgActive R-0 W1S-0 W1C-0 Table 25. Device Status and Command Register Field Descriptions Bit Field Type Reset Description 7:2 RSVD R 0 Reserved Read only, returns 0 when read 1 smbusRst W1S 0 SMBus interface reset This bit loads the registers back to their GRSTz values. This bit is set by writing a 1 and is cleared by hardware on completion of the reset. A write of 0 has no effect. 0 cfgActive W1C 0 Configuration active This bit indicates that configuration of the TUSB4041I device is currently active. The bit is set by hardware when the device enters the I2C or SMBus mode. The TUSB4041I device does not connect on the upstream port while this bit is 1. When in the SMBus mode, this bit must be cleared by the SMBus host to exit the configuration mode and allow the upstream port to connect. The bit is cleared by a writing 1. A write of 0 has no effect. |
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