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UCC24612

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SLUSCM5A – AUGUST 2017 – REVISED FEBRUARY 2018

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Feature Description (continued)

7.3.3.3 SR Turn-on Re-arm

The VG output may only turn on when the controller has been armed for the next switching cycle. The controller

is armed for each successive SR cycle only after TOFFBLANK expires. The TOFFBLANK timer only starts after VD

pin voltage rises 500 mV above the VS pin.

7.3.4 Gate Voltage Clamping

With the wide VDD voltage range capability, UCC24612 clamps the gate driver voltage to a maximum level of 9.5

V to allow fast driving speed, low driving loss and compatibility with different MOSFETs. The 9.5-V level is

chosen to minimize the conduction loss for the non-logic level MOSFETs.

The gate driver voltage clamp is achieved through the regulated REG pin voltage. When VDD voltage is above

9.5 V, the linear regulator regulates the REG pin voltage to be 9.5 V, which is also the power supply of the gate

driver stage. This way, the MOSFET gate is clamped at 9.5 V, regardless of how high the VDD voltage is. When

the VDD voltage is close to or below the programmed REG pin regulation voltage, UCC24612 can no longer

regulate the REG pin voltage. Instead, it enters a pass-through mode where the REG pin voltage follows the

VDD pin voltage with slight voltage drop out (VREGDO). During this time, the gate driver voltage is lower than its

programmed value but still provides SR driving capability. The UCC24612 is disabled once the REG pin voltage

drops below its UVLO level.

7.3.5 Standby Mode

With more stringent efficiency standards such as Department of Energy (DoE) level VI, external power supplies

are expected to maintain very low standby power at no-load conditions. It is essential for the SR controller to

enter the low-power standby mode to help save standby power.

During standby mode, the power converter loss allocation is quite different compared to heavy load. At heavier

load, both conduction loss and switching loss are quite high. However, at light load, the conduction loss becomes

insignificant and switching loss dominates. To help improve standby power, modern power supply controllers

often enter burst mode to save switching loss. Furthermore, in each burst switching cycle, the energy delivered is

maximized to minimize the number of switching cycles needed and further reduce the switching loss.

Traditionally, the SR controller monitors the SR conduction time to distinguish normal operating modes from

standby mode. This criterion is no longer suitable for the modern power supply controller designed for delivering

minimum standby power.

Instead, in UCC24612, a frequency based standby mode detection is used. UCC24612 continuously monitors the

average switching frequency of the SR. Once the average switching frequency of the SR controller drops below

12 kHz, the UCC24612 enters standby mode and reduces its current consumption to IVDDSTBY. During standby

mode, the VG pin is kept low while the SR switching cycle is continuously monitored. Once the average

switching frequency is more than 15 kHz over a 4.5-ms window, the SR operation is enabled again. UCC24612

ignores the first six SR switching cycles after coming out of standby mode to make sure the SR isn't turned on in

the middle of the switching cycle.