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STA335BW 数据表(PDF) 29 Page - STMicroelectronics |
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STA335BW 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 54 page ![]() STA335BW Register description 29/54 5.6 Configuration register F (address 0x05) 5.6.1 Output configuration Note: To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs. D7 D6 D5 D4 D3 D2 D1 D0 EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0 01 0 1 1 1 0 0 Bit R/W RST Name Description 0 R/W 0 OCFG0 Selects the Output Configuration 1 R/W 0 OCFG1 Table 14. Output configuration engine selection OCFG(1..0) Output configuration CONFIG PIN 00 2 Channel (Full-Bridge) Power, 2 Channel Data-Out: 1A/1B →1A/1B 2A/2B →2A/2B LineOut1 →3A/3B LineOut2 →4A/4B Line Out Configuration determined by LOC register 0 01 2(Half-Bridge).1(Full-Bridge) On-Board Power: 1A →1A Binary 0 ° 2A →1B Binary 90° 3A/3B →2A/2B Binary 45° 1A/B →3A/B Binary 0° 2A/B →4A/B Binary 90° 0 10 2 Channel (Full-Bridge) Power, 1 Channel DDX: 1A/1B →1A/1B 2A/2B →2A/2B 3A/3B →3A/3B EAPDEXT and TWARNEXT Active 0 11 1 Channel Mono-Parallel: 3A →1A/1B w/ C3BO 45° 3B →2A/2B w/ C3BO 45° 1A/1B →3A/3B 2A/2B →4A/4B 1 |
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